The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a fully depleted field effect transistor with a thin body formed on a dielectric island in SOI (semiconductor on insulator) technology such that a single implantation step is used to form the drain and source extension regions and the drain and source contact regions.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes spacers 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacers 122 are comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacers 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET 100 are scaled down further, the junction capacitances formed by the drain and source extension junctions 104 and 106 and by the drain and source contact junctions 108 and 112 may limit the speed performance of the MOSFET 100. Thus, referring to FIG. 2, a MOSFET 150 is formed with SOI (semiconductor on insulator) technology. In that case, a layer of buried insulating material 152 is formed on the semiconductor substrate 102, and a layer of semiconductor material 154 is formed on the layer of buried insulating material 152. Elements such as the gate dielectric 116, the gate electrode 118, the spacers 122, and the spacer liner oxide 124 having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function.
A drain extension junction 156 and a source extension junction 158 of the MOSFET 150 are formed in the layer of semiconductor material 154. The drain extension junction 156 and the source extension junction 158 are shallow junctions to minimize short-channel effects in the MOSFET 150 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication. A channel region 160 of the MOSFET 150 is the portion of the layer of semiconductor material 154 between the drain and source extension junctions 156 and 158.
In addition, a drain contact region 162 is formed by the drain extension junction 156, and a source contact region 164 is formed by the source extension junction 158. A drain silicide 166 is formed with the drain contact region 162 to provide contact to the drain of the MOSFET 150, and a source silicide 168 is formed with the source contact region 164 to provide contact to the source of the MOSFET 150. Processes for formation of such structures of the MOSFET 150 are known to one of ordinary skill in the art of integrated circuit fabrication.
The drain contact region 162 and the source contact region 164 are formed to extend down to contact the layer of buried insulating material 152. Thus, because the drain contact region 162 and the source contact region 164 of the MOSFET 160 do not form a junction with the semiconductor substrate 102, junction capacitance is minimized for the MOSFET 150 to enhance the speed performance of the MOSFET 150 formed with SOI (semiconductor on insulator) technology.
Furthermore, during operation of the MOSFET 150, the channel region 160 may be fully depleted when the layer of semiconductor material 154 is relatively thin having a thickness in a range of from about 50 angstroms to about 200 angstroms. When the channel region 160 of the MOSFET 150 is fully depleted, undesired short channel effects of the MOSFET 150 are further minimized, as known to one of ordinary skill in the art of integrated circuit fabrication. However, such a thin layer of semiconductor material 154 is undesirable because a low volume of the drain silicide 166 and the source silicide 168 results in high parasitic series resistance at the drain and the source of the MOSFET 150. Such high parasitic series resistance at the drain and the source of the MOSFET 150 degrades the speed performance of the MOSFET 150.
Thus, a mechanism is desired for forming a field effect transistor in SOI (semiconductor on insulator) technology with drain and source extension regions formed with a thin portion of semiconductor material such that the channel region of the field effect transistor is fully depleted and with drain and source contact regions formed with a thick portion of the semiconductor material to minimize series resistance at the drain and source of the field effect transistor.
Accordingly, in a general aspect of the present invention, a field effect transistor is formed in SOI (semiconductor on insulator) technology with the drain and source extension regions formed with thinner semiconductor material on a dielectric island and with drain and source contact regions formed with thicker semiconductor material disposed to the sides of the dielectric island.
In one embodiment of the present invention, for fabricating a field effect transistor in SOI (semiconductor on insulator) technology, an opening is etched through a first surface of a first semiconductor substrate, and a dielectric material is deposited to fill the opening. The dielectric material and the first surface of the first semiconductor substrate are polished down to form a dielectric island comprised of the dielectric material surrounded by the first surface of the first semiconductor substrate that is exposed. The semiconductor material of the first semiconductor substrate remains on the dielectric island toward a second surface of the first semiconductor substrate. A layer of dielectric material is deposited on a second semiconductor substrate. The first surface of the first semiconductor substrate is placed on the layer of dielectric material of the second semiconductor substrate such that the dielectric island and the first surface of the first semiconductor substrate are bonded to the layer of dielectric material.
The second surface of the first semiconductor substrate is exposed, and a gate dielectric and a gate electrode are formed over a portion of the semiconductor material disposed on the dielectric island on the second surface of the first semiconductor substrate. A drain and source dopant is implanted into the second surface of the first semiconductor substrate that is exposed. A drain extension region and a source extension region are formed by the drain and source dopant being implanted in the semiconductor material disposed on the dielectric island. In addition, a drain contact region and a source contact region are formed by the drain and source dopant being implanted in the semiconductor material of the first semiconductor substrate disposed to sides of the dielectric island.
The present invention may be practiced to particular advantage when the first and second semiconductor substrates are comprised of silicon and when the dielectric island within the first semiconductor substrate and the layer of dielectric material on the second semiconductor substrate are comprised of silicon dioxide (SiO2), according to one embodiment of the present invention.
In this manner, the drain and source extension regions are formed with the thinner semiconductor material on the dielectric island to minimize short channel effects of the field effect transistor. On the other hand, the drain and source contact regions are formed with the thicker semiconductor material to the sides of the dielectric island such that thicker drain and source suicides are formed. With thicker drain and source suicides, the series resistance at the drain and source of the field effect transistor is minimized to enhance the speed performance of the field effect transistor. In addition, the field effect transistor is formed in SOI (semiconductor on insulator) technology such that junction capacitance is minimized for the field effect transistor to further enhance the speed performance of the field effect transistor.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.